1. Field of the Invention
The present invention relates to a flash memory device, and more particularly to a flash memory device and fabrication method thereof for having a contactless and virtual ground structure and being appropriate for a highly integrated flash memory device fabrication.
2. Description of the Prior Art
Referring to FIG. 1, a conventional flash memory device is fabricated as following steps.
As a first step, a plurality of highly concentrated n-type regions 2 each distanced from each other to a certain extent and serving as a buried bit line are formed downwardly from the upper surface of a substrate 1. An oxide thin film is formed on the surface of the substrate 1. On the oxide thin film and between the n-type regions there is formed a mask. The mask is removed after performing a heat treatment thereon. As a result, a field oxide film 3 is formed on the n-type regions 2. On the substrate 1 and between the n-type regions 2 there is formed a gate oxidation film 4.
As a second step, floating gates 5 composed of poly-silicon are each formed on the gate oxide film 4. An insulation film 6 is grown on the floating gate 5 including the field oxide film 3. Then, the fabrication of the conventional flash memory device is completed by forming on the insulation oxide film 6 a control gate 7 using poly-silicon and serving as word lines.
With reference to FIG. 2, the layout of the conventional flash memory device fabricated through the above steps will now be described.
A plurality of buried bit lines shown as the n-type regions 2 in FIG. 2 are arrayed distancing from but parallel to each other. A plurality of word lines shown as the control gates 7 are arrayed vertical to the bit lines but parallel to each other. On each word line between the buried bit lines there are positioned floating gates 5. The field oxide film 3 is provided in overlapping regions between the buried bit lines and the word lines and in between the same. At this time, because contacts are not formed on the buried bit lines, high integration can be realized. Also, the floating gates 5 are symmetrical to left and right. At this time, a virtual ground structure denotes a mechanism in which drain/source regions in a memory cell are defined in accordance with the operation of the memory cell.
Also, to program a selected cell "a" shown in FIG. 1, a high voltage is applied to the control gate 7 and then an electric field is induced between a source region 2a and a drain region 2b, whereby hot electrons controlled by the voltage which is applied to the control gate 7 are excited in the drain region 2b and injected jumping over the gate oxide film 4 into the floating gate 5, whereby the erased cell is programmed to record data signals. The thusly operated programming is known as a hot electron injection technique.
In order to erase a cell for storing new data signals therein, the control gate 7 is regrounded and accordingly the source regions 2a and the drain regions 2b are refloated. Then, a high voltage is applied to the substrate 1 (or a bulk), for thereby eliminating against each block unit the electrons injected in the floating gate 5.
To program the flash memory device by using an FN (Fowler-Nordheim) tunnel technique instead of the hot electron injection technique, a high voltage is applied to the control gate 7 and the drain regions 2b are grounded. At this time, source regions 2a must be floated so as not to be applied to voltage. However, because the cell portion "b" as well as "a" must be concurrently programmed, the FN tunnel technique cannot be applied to the programming in the above structure.
Consequently, the previously described conventional flash memory device has a disadvantage in that despite a high integration property resulting from the contactless bit lines, the FN tunnel technique may not be applied to the programming because the floating gate 5 is symmetrical to the left and right thereof.
In general, a hot electron technique requiring several hundred .mu..ANG. per cell for programming demands much more voltage than in an FN tunnel mechanism.
Conclusively, when a chip area becomes smaller to thereby lead to high integration and concentration, the hot electron technique demanding a relatively high voltage has limits in programming by means of a hot electron technique which characterizes relatively high voltage consumption.